FOR EVALUATIONDOC TORUS-PROG-001REV 2026-07CLASS UAGVIS / programme statusPacketFive
TORUS · Project Document

Implementation status & roadmap

TORUS is an Unattended Air Ground Visual Sensor (UAGVIS) platform. This document tracks the whole system: the fielded TORUS-SN ground node (hardware + Zephyr firmware), the TORUS-MEG gateway and TORUS-CCISRT command layer (concept + datasheets), and the Isaac Sim deployment simulation.

as of 2026-07-05 · repo /opt/repo/TORUS · branch main (3 commits ahead of origin)
Hardware design
TORUS-SN rev pre-prod
CONVERGED
Fully generated KiCad 10 board, routed & polished
Schematic / ERC
0 violations
CLEAN
Netlist mirrors PCB by construction
PCB / DRC
19 violations · 3 unconnected
HAND-FINISH
Mostly waivable; ~10 min GUI cleanup remains
Firmware
Targets previous hardware rev
PORT NEEDED
Zephyr app written for ESP32-C3 / SX1268 board
MEG gateway (cluster-aware)
Concept + datasheet
DESIGN STUDY
Clustering / HA design target; node protocol is gateway-ready
CCISRT command
Runnable, phases 1 to 2.5
RUNNABLE
Roles, telemetry (OpenTelemetry), ingest, store, fusion
Deployment simulation
Isaac Sim starter
RUNNABLE
Portable planner + Isaac scene in torus-isaac-sim

1Implemented: hardware (TORUS-SN)

The current board supersedes the original ESP32-C3/SX1268 concept in the README. It is an 80 × 55 mm 4-layer node: ESP32-S3-WROOM-1 host, LR1110 (LoRa 433 MHz + GNSS + WiFi-scan), OPA2134/MCP4017 geophone AFE with LM393 hardware wake, 2× INMP441 I2S microphones, DS3231 RTC, TP4056 + AMS1117 power, 3× TPS22918 gated rails. 91 parts, 68 nets.

Remaining DRC picture (release board)

FindingCountAssessment
Copper-to-edge clearance5Edge-launch SMA / USB-C pads, by design, waivable
Clearance11Sub-0.2 mm squeezes near the LR1110 fanout, review, likely acceptable
Solder-mask bridges2Cosmetic; check fab's minimum mask sliver
Shorting items1Zone-pair bookkeeping artifact
Unconnected items3LR1110_IRQ, short VCC_LR1110 stub, one zone pair, ~10 min of hand routing

2Implemented: firmware & docs

The firmware/hardware gap is the project's main debt: everything in src/ and boards/ targets the earlier ESP32-C3 + SX1268 + AB1805 + LC76G + SPI-camera design. The built board is ESP32-S3 (Xtensa) + LR1110 + DS3231 + I2S mics + I2C digipot, with no camera. The application architecture carries over; the BSP and every driver binding must be ported.

3Implemented: system docs & simulation

4Pending TODOs

P0: before sending the board to fab

#TaskEffort
0.1Hand-finish the 3 unconnected nets (LR1110_IRQ, VCC_LR1110 stub, zone pair) in the KiCad GUI~10 min
0.2Verify the 6 engineering FLAGS: MINI-1→WROOM-1 substitution impact; USB on GPIO35/36 vs native GPIO19/20; MCP4017, SKY13350, SPF5189Z pin orders; LR1110 pad geometry vs production datasheethours
0.3Decide the USB programming path: move D±to GPIO19/20 or add a USB-UART bridgedesign call
0.4Review AMS1117 quiescent current against sleep-current targets (original spec targeted ~8-9 µA; an LDO swap may be needed)design call
0.5Review the 11 LR1110-area clearance violations against the chosen fab's rules~1 h

P1: firmware port to TORUS-SN

#TaskNotes
1.1New Zephyr board for ESP32-S3 (Xtensa)Replace the RISC-V torus_iot_edge BSP; new device tree from torus_design.py pin map
1.2LR1110 driver integrationLoRa + GNSS scan + WiFi scan; Semtech SWL2001/LR11xx driver port, replaces SX126x path
1.3I2S stereo capture for 2× INMP441New acoustic subsystem; feeds TinyML classification
1.4DS3231 RTC supportReplaces AB1805 handler; wire 32 kHz output usage for LR1110 GNSS
1.5MCP4017 gain control over I2CReplaces SPI MCP41010 driver
1.6Wake-on-seismic path (LM393 → GPIO wake) and TPS22918 rail gatingDeep-sleep state machine update
1.7Retire camera supportTORUS-SN carries no camera; drop the Arducam code path
1.8Battery telemetry via ADC_VBAT dividerNew on this rev (R29/R30)

P2: system & housekeeping

#TaskNotes
2.1TORUS-MEG gateway detailed design & buildTake the datasheet concept to schematic/PCB; 433 MHz concentrator, Jetson carrier, power; implement cluster membership, leader election, and HA failover; P2P vs LoRaWAN decision pending
2.1bTORUS-CCISRT command software buildFusion core + COP + field app from the C2 datasheet; define the SN/MEG event schema first
2.2Enclosure designAutodesk Fusion, importing hw/3d_models/TORUS-SN.step
2.3Update README to the TORUS-SN architectureStill documents the superseded ESP32-C3/SX1268 design
2.4gen_bom.py, BOM with manufacturer part numbersPlanned in torus_design.py header; current BOM is value/footprint only
2.5Push the 3 unpushed commits on mainKiCad 10 migration + GLB export work
2.6Bring-up & validation plan executionPower, peripherals, AFE calibration, LoRa range, GNSS TTFF, sleep-current measurement (README §9)
2.7Isaac Sim twin: terrain import + physics seismicExtend torus-isaac-sim beyond the starter: GIS/heightmap terrain, PhysX-based detection, visual-mast sensors
2.8SN-V2 SDR carrier hardware designDesign brief done (hw/variants/sn-v2-sdr.md); Zynq + AD9363 phase 1 carrier stacked on the V1 board; no schematic/PCB yet
2.9SN-V3 wired optical hardware designDesign brief done (hw/variants/sn-v3-optical.md); host swap for RMII EMAC + 100BASE-FX PHY, or ADIN1110 T1L fallback; no schematic/PCB yet
2.10SN-V4 transducer interlock daughterboardDesign brief done (hw/variants/sn-v4-transducer.md); hardware three-condition interlock, fail-safe de-energized; no schematic/PCB yet

5Toolchain reference

PieceLocation / command
KiCad 10 (AppImage)/opt/kicad · wrappers: kpython, kcli.sh (setup-kicad10.sh)
Full hardware buildhw/build.sh  (REUSE_SES=1 skips ~3 min routing)
Best-of-N releasehw/release.sh
Schematic + BOMhw/build_sch.sh
Firmware buildwest build -b torus_iot_edge

Pipeline gotchas already solved (encoded in the scripts, don't fight them): zone fill must run as a subprocess on the saved board; kicad-cli exports without refilling zones; Freerouting hangs on stacked pre-placed vias; several library footprints ship board-blanketing antenna keepouts that must be stripped.

Trademarks & third-party notice. TORUS is an independent platform. Company names and product model numbers referenced in this document (including but not limited to Semtech, Teledyne FLIR, R.T. Clark, InvenSense, Texas Instruments, Microchip, Espressif, Analog Devices / Maxim Integrated, and NVIDIA) are used solely for engineering and bill-of-materials identification and imply no affiliation with or endorsement by those companies. Supply of any such third-party product or component to the designers, manufacturers, integrators, or evaluators of the TORUS platform remains at the sole discretion of the respective owning company, organisation, or legal entity. All trademarks are the property of their respective owners.