Four programmes, each built from scratch and developed the way the Linux kernel is: a rack-scale emulation platform, a computer architecture, an in-kernel execution engine, and a secure packet-processing system on chip. Each is open source, and each is at a different point on the road to publication.
Cnuas
A software-defined AI/HPC rack-scale emulation platform and hyperscale data center facility twin.
Cnuas is a fully software-emulated AI and HPC infrastructure. Virtual GPUs, a virtual GPU-peer fabric, virtual InfiniBand and RoCE switches and virtual RDMA NICs, all built from scratch and developed the way the Linux kernel is, so unmodified Linux guests run real distributed workloads on simulated silicon.
PDP-V
An incarnation of the PDP-11 soul in the physical realm of RISC-V.
PDP-V is a computer architecture and the experimental apparatus for a falsifiable hypothesis: whether PDP-11 style operand orthogonality, combined with vector-length-agnostic execution, improves the workloads that AI infrastructure actually runs. It defines a whole architecture contract rather than an instruction set alone, covering the unprivileged and privileged architecture, memory and platform contracts, accelerators and conformance, and it carries that contract through to a QEMU machine model, synthesisable RTL, a toolchain and a Linux port.
MERLIN-V
An in-kernel JIT virtual machine whose bytecode is the RISC-V instruction set.
MERLIN-V is a from-scratch design of an in-kernel virtual machine in the same territory as eBPF, with one decisive change: programs are encoded in a restricted profile of the RISC-V instruction set rather than in a bespoke bytecode. On a RISC-V host that removes translation entirely, since the bytecode already is the host's native instruction set: verify, relocate, flush the instruction cache and jump. On other hosts a translating JIT consumes stock RISC-V machine code instead of a private format.
KESTREL-V
A RISC-V packet-processing system on chip with eBPF execution in hardware.
KESTREL-V is a CVA6-based system on chip built around a Keystone coprocessor that runs eBPF programs in eight isolated execution slots, each a PicoRV32 nano-controller running a uBPF interpreter. The design covers the coprocessor and its register map, DMA and mailbox control, the system memory map, a custom instruction set extension for coprocessor control, and the route to running it, through a QEMU model, a Linux board support package and synthesis onto a PolarFire SoC FPGA.
All four projects are under active research and release preparation. Source repositories, upstream contribution series, publications, research data, and reproducibility artifacts are not yet publicly available. Each project's availability page carries the status of every item and is updated as each becomes public.
For collaboration, or to be notified when artifacts are released, please get in touch.