CnuasGPU, Datasheet
| Item |
Value |
| Part |
cnuasgpu |
| Type |
SIMT virtual GPU accelerator |
| Version |
v0.2.0-14-ga157b80-dirty |
| Repo |
PacketFive/CnuasGPU |
1. Overview
CnuasGPU is the emulated GPU accelerator of the Cnuas platform. It presents a
QEMU PCIe device with a SIMT (single-instruction, multiple-thread) execution
model, a portable CnuasIR instruction set, and a CUDA-style runtime
(libcnuasrt). Kernels are dispatched to the best available host SIMD backend
(AVX-512, AVX2, or scalar) selected at runtime, giving GPU-like compute on
commodity CPUs.
Key features
- SIMT execution model with 32-thread warps.
- CnuasIR portable ISA (RVV 1.0 subset plus Cnuas tensor opcodes).
- Multi-architecture compute backends with runtime dispatch and env-var override.
- CUDA-style runtime (
libcnuasrt) over a low-level driver shim (libcnuasdev).
- Tensor MAC unit per SM for matmul / AI workloads.
- Native CnuasLink endpoint for GPU-to-GPU fabric traffic.
cnuassmi / cnuas-smi inventory and telemetry.
2. Device block diagram
flowchart TB
subgraph GPU["cnuasgpu device (default config)"]
direction TB
subgraph SMS["16 x Streaming Multiprocessor (SM)"]
direction LR
SM0["SM: 32 ALU lanes<br/>1 tensor MAC<br/>1 warp sched<br/>1 SFU<br/>64 KB regfile<br/>128 KB L1/shared"]
end
L2["L2 cache (8 MB)"]
HBM["Device memory (8 GB, HBM model)"]
LINK["CnuasLink endpoint (4 lanes)"]
SMS --> L2 --> HBM
SMS --> LINK
end
subgraph BARS["PCIe BARs"]
direction LR
BAR0["BAR0: 64 KB MMIO regs"]
BAR1["BAR1: device mem window (<=16 GB)"]
BAR2["BAR2: 4 KB doorbell pages"]
end
BARS --- GPU
classDef s fill:#fce7f3,stroke:#9d174d,color:#831843
classDef m fill:#dbeafe,stroke:#1e40af,color:#1e3a8a
class SM0,SMS s
class L2,HBM,LINK,BAR0,BAR1,BAR2 m
3. Functional specifications
| Parameter |
Value |
| PCI vendor : device ID |
0x1AF4 : 0x10F1 |
| Execution model |
SIMT, 32-thread warps |
| ISA |
CnuasIR (RVV 1.0 subset + tensor opcodes) |
| Streaming Multiprocessors (SM) |
16 (default configuration) |
| Vector ALU lanes / SM |
32 |
| Tensor MAC units / SM |
1 |
| Warp schedulers / SM |
1 |
| Special function units / SM |
1 |
| Register file / SM |
64 KB (~1 cycle) |
| L1 / shared memory / SM |
128 KB (~30 cycles) |
| L2 cache (chip-wide) |
8 MB (~200 cycles) |
| Device memory (HBM model) |
8 GB (~500 cycles) |
| CnuasLink endpoint |
4 lanes (default) |
| Char device |
/dev/cnuasgpu0, /dev/cnuasgpu1, … |
4. Kernel driver features (cnuasgpu.ko)
Single char-device driver (src/cnuasgpu/driver/cnuasgpu.c) exposing /dev/cnuasgpuN.
4.1 ioctl interface
| ioctl |
Purpose |
CNUASGPU_IOC_INFO |
Query device properties (SM count, memory, IDs) |
CNUASGPU_IOC_ALLOC |
Allocate device memory |
CNUASGPU_IOC_FREE |
Free device memory |
CNUASGPU_IOC_MEMCPY |
Host↔device / device↔device copy |
CNUASGPU_IOC_LINK_STATUS |
Query CnuasLink endpoint status |
CNUASGPU_IOC_LINK_SEND |
Send a CnuasLink frame to a peer GPU |
CNUASGPU_IOC_LINK_RECV |
Receive a CnuasLink frame from a peer GPU |
4.2 Memory / doorbell
mmap() of BAR1 exposes the device-memory window to userspace.- BAR2 doorbell pages signal work submission; BAR0 holds MMIO control registers.
- MSI-X interrupts deliver completion and CnuasLink events.
5. Runtime / userspace features
Two libraries, layered CUDA-style over the driver.
5.1 libcnuasrt.so, CUDA-Runtime-style API
| Function |
Purpose |
cnuasInit / cnuasShutdown |
Runtime lifecycle |
cnuasGetDeviceCount |
Enumerate GPUs |
cnuasGetDevice / cnuasSetDevice |
Current device selection |
cnuasGetDeviceProperties |
Device capability query |
cnuasMalloc / cnuasFree |
Device memory management |
cnuasMemcpy |
Host↔device / device↔device transfers |
cnuasDeviceSynchronize |
Barrier / completion wait |
cnuasSgemm |
Single-precision GEMM primitive |
cnuasGetErrorString |
Error decoding |
5.2 libcnuasdev.so, low-level driver shim
| Function |
Purpose |
cnuasdev_open / cnuasdev_close |
Open/close /dev/cnuasgpuN |
cnuasdev_get_device_count |
Device enumeration |
cnuasdev_query_info |
CNUASGPU_IOC_INFO wrapper |
cnuasdev_alloc / cnuasdev_free |
CNUASGPU_IOC_ALLOC / FREE wrappers |
cnuasdev_memcpy |
CNUASGPU_IOC_MEMCPY wrapper |
cnuasdev_mmap / cnuasdev_munmap |
BAR1 device-memory mapping |
cnuasdev_status_str |
Status decoding |
6. Compute backends & dispatch
Kernels are implemented behind a cnuas_compute_ops vtable; the loader picks a
backend at runtime.
| Host ISA |
Backend |
Source |
Vector width |
| x86-64 |
AVX-512 |
lib/compute/x86_avx512/ |
512-bit |
| x86-64 |
AVX2 |
lib/compute/x86_avx2/ |
256-bit |
| Portable |
scalar |
lib/compute/scalar/ |
reference/fallback |
The loader in lib/compute/loader/loader.c selects the best backend
automatically, preferring AVX-512 over AVX2 over scalar. Four environment
variables override that choice.
| Variable |
Effect |
CNUAS_COMPUTE_BACKEND |
Force a specific backend |
CNUAS_COMPUTE_LIST |
List available backends |
CNUAS_COMPUTE_VERBOSE |
Verbose selection logging |
7. GPU-to-GPU peer copy flow
sequenceDiagram
autonumber
participant App_A as GPU app (vm-a)
participant Cart_A as libcnuasrt (vm-a)
participant CnuasGpu_A as cnuasgpu.ko (vm-a)
participant CnuasLink as cnuasgpu-link-switchd
participant CnuasGpu_B as cnuasgpu.ko (vm-b)
participant App_B as GPU app (vm-b)
App_A->>Cart_A: peer copy (dst_gpu=1)
Cart_A->>CnuasGpu_A: ioctl CNUASGPU_IOC_LINK_SEND
CnuasGpu_A->>CnuasLink: 12B header + payload {type=DATA, src=0, dst=1}
CnuasLink->>CnuasLink: FDB lookup by dst_gpu
CnuasLink->>CnuasGpu_B: framed payload
CnuasGpu_B-->>App_B: peer data visible in dest buffer
8. Interfaces
| Interface |
Description |
| Host bus |
QEMU PCIe device (cnuasgpu), advertises PCIe Gen5 x16 |
| BAR0 |
64 KB MMIO control registers |
| BAR1 |
Device memory window (up to 16 GB, configurable) |
| BAR2 |
4 KB per-context doorbell pages |
| Char device |
/dev/cnuasgpu0, /dev/cnuasgpu1, … |
| GPU fabric |
CnuasLink endpoint (see CnuasLink) |
9. Software support
| Item |
Value |
| Runtime |
libcnuasrt.so (CUDA Runtime-style API) |
| Low-level driver |
libcnuasdev.so |
| Compute primitives |
vector add, tiled SGEMM (AVX2 / AVX-512) |
| Tools |
cnuassmi / cnuas-smi (device inventory + telemetry) |
| Design reference |
CnuasGPU Design |
| Item |
Value |
| Repo |
PacketFive/CnuasGPU |
| Submodule path |
src/cnuasgpu (in PacketFive/cnuas) |
| Version |
v0.2.0 |
| Language |
C (GNU C) + host SIMD intrinsics |
11. Revision history
| Revision |
Date |
Notes |
| A |
2026-07-05 |
Initial datasheet |
| B |
2026-07-05 |
Added block diagram, ioctl/runtime tables, compute-backend dispatch, peer-copy flow |